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喬建民:材料創新技術的專家
--記第四屆“杭州市僑界十大傑出人物”喬建民先生
發佈時間:2016-02-13

 

  喬建民,生於1960年2月,杭州漢宇科技有限公司總經理。
  喬博士1982年就讀于浙江大學材料係;1989年獲得羅馬大學和浙江大學材料科學博士學位;1989年浙江大學材料係教師;1991年赴美在Santa Clara 大學做博士後研究,並與1992年創辦美國高科技研究生教育的國際科技大學;1996年在美國的應用材料公司任資深工程經理;1998年任美國Cypress半導體公司研發總工程師;2000年創辦美國先進光通信公司;2002年創辦美國HQ科技公司;2004年出任美國PicoNetics公司運營總監;2005年回國,在杭州創辦了漢力國際微電子有限公司2009年創辦杭州漢宇科技有限公司。喬建民博士是材料工程學、微電子工程學專家,浙江省海創會副會長、浙江大學校友總會理事、浙江大學海創俱樂部常務副理事長,曾任美國北加州浙大校友會會長,在當地僑界有很大的影響力。他目前也是蕭山開發區高級經濟顧問。
  喬博士1988年研發出的非晶硅太陽能電池的能量轉換效率曾創造了歐洲最高記錄, 並製造出了世界上第一隻非晶硅高能粒子探測器。1990和1991年喬博士被我國國務院和國家教育部任命為作出傑出貢獻的年輕科學家和優秀年輕教師。1994年至2000年在美學習工作期間,研發出了多項微電子工程創新技術, 1994年被美國政府認定為具有卓著能力的科學家。2001年至2008年研發出了多項奈米材料創新技術。2005年喬博士參與了以《基於能量回收原理的微電子超低功耗機理研究》為課題的國家973計劃;同時喬博士擁有20個美國專利和多項歐洲日本和台灣專利。
  1.奈米硅改性雙組份耐磨滲透硬化劑及其製備方法。中國專利受理號:201410172177.X
  2.倣大理石材料乾粉及高光防滑倣大理石地坪的施工方法。中國專利受理號:201410171661.0
  3.J. Chen, J. Chen; and J. Qiao, Semiconductor processing chamber substrate holder method and structure, US Patent#: 6,865,065, March 8, 2005.
  4.W. Branco and J. Qiao, Method for cleaning plasma etch chamber structures, US Patent#: 6,841,008, January 11, 2005.
  5.J. Qiao, S. Geha, and M.G. Sediegh, Method of forming self aligned contacts, US Patent#: 6,803,318, October 12, 2004.
  6.B. Jin, J. Qiao and S. Sharifzadeh, Semiconductor structure and method of making contacts in a semiconductor structure, US Patent #: 6,734,108, May 11, 2004.
  7.M.G. Sedigh, J. Qiao, and S. Geha, Method for etching a dielectric layer formed upon a barrier layer, US Patent #: 6,693,042, February 17, 2004.
  8.A. Blosse, S. Thedki, J. Qiao, and Y. Gilboa, Method of making metallization and contact structures in an integrated circuit, US Patent #: 6,635,566, October 21, 2003.
  9.Z. Wan, J. Chen; Jiong, P. Ling; Peiching, and J. Qiao, Apparatus and method for uniformly depositing thin films over substrates, US Patent #: 6,579,420, June 17, 2003.
  10.A. Blosse, S. Thekdi, J. Qiao, and Y. Gilboa, Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer, US Patent #: 6,399,512, June 4, 2002; also European Patent #: EP1164637, December 19, 2001; also Japan Paten #: JP2002016140, January 18, 2002.
  11.L. Murugesh, M. Orczyk, P. Narawankar, J. Qiao, and T. Sahin, Sequential in-situ heating and deposition of halogen-doped silicon oxide, US Patent #: 6,375,744, April 23, 2002.
  12.J. Qiao, J. Nulty, P. Arleo, and S. Salimian, Electrostatic or mechanical chuck assembly conferring improved temperature uniformity onto workpieces held thereby, workpiece processing technology and/or apparatus containing the same, and method(s) for holding and/or processing a workpiece with the same, US Patent #: 6,373,679, April 16, 2002.
  13.J. Qiao, S. Thekdi, M. Rathor, and J. Nulty, Plasma-etch chemistry and method of improving etch control, US Patent #: 6,372,634, April 16, 2002.
  14.B. Jin and J. Qiao, Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device, US Patent #: 6,350,665, February 26, 2002.
  15.S. Thekdi, A. Blosse, Y. Gilboa, and J. Qiao, Method of making metallization and contact structures in an integrated circuit, European Patent #: EP1168434, February 1, 2002; also Japan Patent #: JP2002016139, January 18, 2002.
  16.J. Qiao and S. Thekdi, Method for conditioning a plasma etch chamber, US Patent #: 6,322,716, November 27, 2001.
  17.L. Murugesh, M. Orczyk, P. Narawankar, J. Qiao, and T. Sahin, Sequential in-situ heating and deposition of halogen-doped silicon oxide, US Patent #: 6,228,781, May 8, 2001.
  18.J. Qiao and J. Nulty, Method and structure for making self-aligned contacts, US Patent #: 6,214,743, April 10, 2001.
  19.P. Narwankar, L. Murugesh, T. Sahin, M. Orczyk, and J. Qiao, High deposition rate recipe for low dielectric constant films, US Patent #: 6,136,685, October 24, 2000; also Japan Patent #: JP10340900, December 22, 1998.
  20.J. Qiao and J. Feng, Method of reducing impurity contamination in semiconductor process chambers, US Patent #: 5,976,900, November 2, 1999.
  21.J. Zhao, T. Cho, X. Guo, A. Tabata, J. Qiao, and A. Schreiber, Method of reducing residue accumulation in CVD chamber using ceramic lining, US Patent #: 5,885,356, March 23, 1999, also European Patent #: EP0780490, June 25, 1997; also Japan Patent #: JP9251992, September 22, 1997.
  22.J. Qiao, C. Chan, C. Leung, D. Chan, and T. Sahin, Method and apparatus for seasoning a substrate processing chamber, Taiwan Patent #: TW416100; also European Patent #: EP0892083, January 19, 1999; also Japan Patent #: JP11067746, March 9, 1999.

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